Meet GUC at Embedded World Nuremberg: Advanced ASIC Design for Next-Generation Systems

ASIC Design at Embedded World and Why It Matters

Embedded World 2026 represents the global convergence of embedded systems engineers, silicon designers, and technology innovators shaping the future of computing. Held annually in Nuremberg, this benchmark conference attracts over 35,000 professionals and more than 1,200 exhibitors across automotive, industrial IoT, high-performance computing, and consumer electronics sectors.

For silicon design professionals, Embedded World is more than a trade show. It is a critical platform to evaluate emerging technologies, meet manufacturing partners, and discover solutions to design challenges that no generic component can address. The 2026 event promises particular emphasis on artificial intelligence acceleration, automotive autonomous systems, and advanced computing architectures - precisely the domains where custom ASIC design determines competitive advantage.

Who is GUC and Why They Matter to Your Next Project

Global Unichip Corporation (GUC) stands as one of Asia's leading application-specific integrated circuit design services providers. Established in 1998 and headquartered in Hsinchu Science Park, Taiwan, GUC has evolved from a specialist ASIC house into a comprehensive silicon innovation company. The company's significance is underscored by TSMC's 34.8% shareholding, positioning GUC as a formal TSMC Value Chain Alliance (VCA) partner - a designation reserved for only the most strategically important design services firms.

With 855 employees distributed across design centres in Japan, Vietnam, Israel, Europe, North America, and Taiwan, GUC delivers what competing design houses struggle to provide: seamless integration across advanced process nodes (from N7 to N3), mastery of chiplet technology, and production-proven solutions at scale. The company ships over 35 million chips annually across 30+ product tape-outs, demonstrating execution capability that extends far beyond conceptual innovation.

The Critical Challenge GUC Solves: Moving Beyond Monolithic Chip Design

Modern engineering teams face a profound architectural challenge. Traditional monolithic chip design, placing all functionality on a single piece of silicon, introduces unavoidable trade-offs:

Performance vs Power: Consolidating multiple functions pushes power consumption to unacceptable levels. Yield vs Cost: Larger dies suffer from reduced yield, driving unit costs prohibitively high. Design Complexity: Integration of specialised functions (compute, memory, interconnect, control) demands expertise across incompatible design domains. Time to Market: Monolithic designs require sequential engineering, extending development timelines by 18-24 months.

GUC's revolutionary approach: chiplet architecture disaggregating system functions into optimised, independently designed dies, then integrating them using advanced multi-die packaging technologies.

GUC's Technological Foundation: Advanced Chiplet and Interconnect IP

HBM3 Memory IP: World-First Silicon Validation

GUC achieved a historic milestone as the world's first design services company to demonstrate production-ready HBM3 (High Bandwidth Memory) IP across multiple advanced nodes. The significance cannot be overstated:

Performance Metrics:

• N7 variant operates at 7.2 Gbps per pin

• N5 variant delivers 8.4 Gbps per pin

• N3 variants are in upcoming production deployment

• Delivered across 7 product chips using CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging

HBM3 integration transforms system capabilities. Traditional DRAM operates at approximately 50 GB/s bandwidth. HBM3 systems achieve 800+ GB/s, enabling AI models to execute matrix operations that would be impossible with conventional memory architectures. For design engineers working on AI accelerators, machine learning inference engines, or high-performance compute clusters, HBM3 integration fundamentally changes what becomes technically feasible.

Die-to-Die Interconnect: GLink and UCIe Technology

GUC's proprietary GLink technology provides the silicon "nervous system" connecting chiplets with performance characteristics previously impossible to achieve.

GLink-2.5D Performance

• Throughput: 5 Tbps per millimetre of interconnect width

• Power efficiency: 0.3 picojoules per bit

• Latency: 5 nanoseconds end-to-end

• Packaging: InFO (Integrated Fan-Out) and CoWoS compatible

GLink-3D Performance

• Die-on-die stacking within a single chiplet package

• 9 Tbps/mm² cross-sectional throughput

• Enables vertical processor stacking for extreme computational density

Advanced Packaging Technology: CoWoS, InFO, and SoIC

GUC's packaging expertise encompasses the full spectrum of multi-die integration approaches.

Chip-on-Wafer-on-Substrate (CoWoS): Premium packaging enabling chiplets to communicate at gigahertz frequencies with minimal latency penalty.

Integrated Fan-Out (InFO): Cost-optimised packaging redistributing interconnect patterns across organic substrate layers.

System-on-Integrated-Circuit (3D SoIC): Die-stacking within a unified package, achieving extreme integration density.

GUC's Service Delivery: From Customer Specification to Finished Goods

GUC's value proposition extends beyond IP licensing into comprehensive design service delivery. The business model addresses the reality that most engineering organisations lack sufficient internal expertise to execute chiplet designs independently.

Service Scope encompasses:

Specification and Architecture: Translating customer requirements into chiplet-level partitioning strategies, identifying optimal die division points that maximise yield whilst minimising interconnect overhead.

SoC Design: Full-custom SoC development across all process nodes, including logic design, embedded memory, analogue/mixed-signal blocks, and hardware security integration.

Physical Implementation: Placement and routing, signal integrity analysis, power integrity verification, thermal management, and design-for-test (DfT) integration.

Interposer and Redistribution Layer (RDL) Design: Custom substrate and interposer design optimising electrical and thermal characteristics for multi-die systems.

Simulation and Verification: SI/PI/IR/thermal co-simulation validating performance across manufacturing variation and temperature extremes.

Production Enablement: Mask generation, yield analysis, process design kit (PDK) interaction, and manufacturing coordination with TSMC and packaging partners.

Real-World Applications: Where GUC Chiplet Technology Creates Competitive Advantage

Artificial Intelligence Acceleration

AI workloads demand memory bandwidth exceeding any single compute die's ability to sustain. GUC's HBM3 + GLink-2.5D combinations enable:

• Inference Engines: Deploying trained neural networks with memory bandwidth matching computational demand

• Training Acceleration: Multi-die designs distributing training workloads across compute chiplets whilst HBM3 serves as unified memory

• Edge AI Systems: Cost-optimised configurations combining compute specialisation with memory pooling

Recent deployments include N5 AI products using HBM3 with CoWoS, with N3 HPC designs scheduled for Q4 2024 tapeout.

Automotive Advanced Driver Assistance Systems (ADAS)

Autonomous vehicle platforms require simultaneous sensor processing (cameras, lidar, radar), real-time decision algorithms, and safety-critical control. Monolithic designs cannot optimise all domains simultaneously. GUC's approach:

• Sensor Processing Chiplet: Optimised for image processing throughput and latency

• Compute Chiplet: Running inference algorithms with specialised neural processing

• Safety Chiplet: Dedicated to redundancy verification and fail-safe operation

• Memory Subsystem: Unified HBM3 serving all chiplets with QoS guarantees

GUC has delivered ADAS SoCs across N5 and N3 process nodes, with automotive qualification (AEC-Q100 Grade-2) enabling tier-one automotive supplier deployment.

High-Performance Computing Infrastructure

Data centre accelerators (GPU successors, AI chips, specialised processors) drive enormous revenue pools. GUC enables:

• Distributed Compute: Multiple processor chiplets sharing unified memory

• Extreme Memory Bandwidth: HBM3 stacks delivering 800+ GB/s to compute elements

• Thermal Management: Advanced packaging isolating heat generation and enabling passive cooling at higher power densities

• Ecosystem Compatibility: UCIe standardisation enabling interoperability with components from other vendors

What to Expect on the Ineltek Stand at Embedded World

GUC's presence at Embedded World 2026 showcases production-proven technology through four distinct exhibition demonstrations, each illustrating real-world chiplet success and advanced packaging capabilities.

FuriosaAI RNGD: AI Acceleration Card (Live Demo)

The centrepiece demonstration features GUC's collaboration with FuriosaAI on RNGD, positioned as the most efficient AI accelerator for large language models. This functioning multi-die system integrates two HBM3 stacks (48 GB, 1.5 TB/s bandwidth) with a 5600M-gate compute chiplet manufactured at TSMC 5nm. The board operates at 150 W thermal design power and delivers 512 TOPS (INT8) to 1024 TOPS (INT4) compute performance. Visitors can observe real-time inference workload execution and discuss how GUC's design-to-production services enabled FuriosaAI's first-time silicon success.

PEZY Supercomputer HPC Board (Live Demonstration)

A second showcase features GUC's partnership with PEZY on high-performance computing accelerators. The PEZY-SC3 board demonstrates a 512-core custom instruction set processor running at 1.0 GHz, coupled with HBM2 memory delivering 614.4 GB/s bandwidth. PEZY-SC3 provides 2.0 TFLOPS double-precision performance, whilst the advanced PEZY-SC3 variant achieves 4096 cores at 1.2 GHz delivering 19.7 TFLOPS, demonstrating GUC's capability to solve extreme-scale design challenges including massive die area (close to reticle size), extreme thermal design power management, and multi-die HBM integration using CoWoS technology.

ASPEED Remote Management Server Processor (Interactive)

A third demonstration showcases the AST2750 Remote Management Server Processor, illustrating GUC's long-term partnership with ASPEED on advanced baseboard management controller (BMC) solutions. This example demonstrates how GUC integrates high-performance ASIC design with server infrastructure requirements, combining quad-core ARM Cortex-A35 processors at 1.6 GHz with dual ARM Cortex-M4 cores at 400 MHz, DDR5 DRAM support at 3200 Mbps, PCIe Gen4 connectivity, and comprehensive remote presence capabilities. The partnership exemplifies GUC's ability to support AI server development, edge computing, and hyperscale data centre infrastructure.

UCIe 32G PHY IP Silicon Demonstration (Technical Display)

A fourth showcase presents GUC's world-first UCIe 32G PHY IP implementation, demonstrating standards-based chiplet interconnect validated at 32 Gbps per lane with beach bandwidth density of 10 Gbps/mm. The live demonstration includes 32 Gbps eye diagram display showing signal integrity and performance margins, TSMC CoWoS-R packaged test chip with 4-module interconnect demonstrating practical integration of standards-based interconnect in production packaging, and architecture details supporting AXI, CXS, and CHI bus bridges enabling ecosystem interoperability across chiplet designs from multiple partners.

GUC UCIe/GLink-3D N2P Interface (Technical Specification)

Additional technical documentation showcases GUC's world-first GLink/UCIe-3D interface implemented in TSMC N2P process. This cutting-edge die-on-die stacking technology delivers 50 Tbps/mm² full duplex (100 Tbps aggregated) throughput enabling extreme computational density through vertical chiplet stacking, extremely low power consumption below 0.03 picojoules per bit critical for thermal management in multi-die systems, and extremely low latency below 0.5 nanoseconds preserving performance across die-stacking boundaries. The demonstration illustrates how GUC remains at the absolute frontier of advanced packaging technology, with silicon-proven implementations in both standards-based (UCIe) and proprietary (GLink) interconnect approaches.

Throughout the stand, direct technical consultation is available with GUC's system architects, design managers, and application engineers, enabling engineers to discuss how these demonstrated capabilities could address their specific chiplet design challenges.

Who Should Book a Meeting with GUC at Embedded World?

GUC's services deliver exceptional value for specific engineering scenarios:

Design Teams Facing Monolithic Design Constraints: If your product roadmap demands performance or power characteristics unachievable within a single die, chiplet architecture conversations are essential.

Companies Developing AI-Specific Hardware: Inference engines, training accelerators, and edge AI systems benefit disproportionately from GUC's HBM3 and multi-die expertise.

Automotive Suppliers Pursuing ADAS and Autonomous Capabilities: GUC's automotive ASIC pedigree and production experience across N5/N3 nodes provides direct competitive advantage.

Memory-Bandwidth-Constrained Applications: If system performance is fundamentally limited by memory throughput, HBM3 integration discussions are immediately relevant.

Long-Lifecycle Product Programs: GUC's TSMC VCA partnership and commitment to 10+ year supply availability provides supply chain stability unavailable through standard semiconductor channels.

Beyond the Trade Show: Building Long-Term Partnerships

Embedded World meetings catalyse relationships, but GUC's real value emerges through sustained engagement. Initial conversations at Embedded World can transition to:

Feasibility Studies: 2-4 week evaluations examining whether chiplet architecture benefits your specific application, identifying optimal die partitioning strategies, and developing preliminary cost models.

Design Exploration: 8-12 week phases developing preliminary architectural models, simulating performance across manufacturing variation, and refining cost assumptions.

Full Development Programmes: 18-36 month engagements executing complete design-to-production delivery, with GUC providing all engineering resources from specification through manufacturing ramp-up.

Call to Action: Meet GUC at Embedded World 2026

Embedded World 2026 (10-12 March, Nuremberg, Hall 3A, Stand 3A-417) represents a unique opportunity to evaluate GUC's technology in person, discuss your project's specific challenges, and explore partnership possibilities.

Option 1: Book a Pre-Scheduled Meeting Contact Ineltek to arrange a dedicated meeting slot with GUC's technical team. Pre-scheduled conversations ensure focused discussion of your specific challenges.

Option 2: Request Event Attendance Tickets We have an allocation of tickets for promoting to our audience - so please get in touch and see if we can help.

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FAQs - GUC's Custom ASIC Capabilities

Q: How does chiplet design differ from traditional monolithic ASIC development?

A: Monolithic designs place all functionality on a single die, resulting in manufacturing yield loss as die size increases, power density challenges, and design complexity that extends timelines. Chiplet designs partition functionality across optimised dies integrated using advanced packaging. This approach improves yield, enables specialised design for each chiplet's function, and accelerates development by enabling parallel engineering streams.

Q: What is HBM3 and why does it matter?

A: HBM3 (High Bandwidth Memory generation 3) is a vertically stacked DRAM architecture delivering 800+ GB/s bandwidth compared to conventional DRAM's 50 GB/s. For AI systems, this dramatic bandwidth improvement means neural network inference executes 10-15 times faster than memory-bound performance would permit. GUC's world-first silicon-validated HBM3 IP eliminates integration risk for customers developing AI accelerators.

Q: What's the timeline for developing a chiplet-based ASIC with GUC?

A: Feasibility studies require 2-4 weeks. Architectural exploration spans 8-12 weeks. Full design-to-production programmes typically require 18-36 months depending on complexity and process node. GUC's experience executing 30+ tape-outs annually demonstrates execution capability at scale.

Q: How does cost compare to monolithic ASIC designs?

A: Chiplet designs typically reduce non-recurring engineering (NRE) costs by 30-40% through parallelised design, IP reuse, and optimised process node selection. Unit costs depend on volume and complexity, but advanced packaging costs decline rapidly as production ramps. GUC's TSMC VCA partnership provides privileged access to packaging capacity and cost structures.

Q: What's the difference between GLink and UCIe interconnect?

A: GLink is GUC's proprietary technology optimised for maximum performance within 2.5D and 3D packaging. UCIe is an industry standard supported by multiple foundries and fabless companies, enabling ecosystem interoperability. GUC supports both, allowing customers to choose based on their specific requirements.

Q: Is automotive qualification available?

A: Yes. GUC has delivered AEC-Q100 Grade-2 ADAS SoCs at N5 and N3, demonstrating full automotive qualification capability. ASIL-D functional safety integration is supported across all design services.

Q: How does GUC manage intellectual property in chiplet designs?

A: GUC respects customer IP through formal confidentiality agreements, isolated design teams, and secure design tools infrastructure. Customer designs remain confidential and are never shared across projects.