How to Improve Thermal Performance in High-Power SiC MOSFET Designs: A Comparison of 1200V and 1700V Solutions

Introduction – Why Thermal Loss Remains the Silent Killer in Power Electronics

Heat remains one of the most limiting factors in high-power converter design. In industrial drives, EV traction inverters, UPS systems, and PV inverters, 30–50 per cent of system losses ultimately become heat. As switching frequencies rise and power densities increase, designers face shrinking thermal margins.

Silicon MOSFETs reach their limits quickly under these conditions. SiC MOSFETs offer the required combination of low RDS(on), reduced switching loss, and stable behaviour at elevated temperatures. But not all SiC platforms perform equally.

FUYI’s 1200 V and 1700 V SiC MOSFET families deliver strong thermal benefits through:

• Low specific on-resistance

• Excellent switching Figures of Merit

• Ultra-low leakage current (IDSS)

• Packaging and bare-die options suited to thermal optimisation

This article highlights the essential thermal behaviours engineers must understand, followed by a comparison of FUYI’s platforms against competitive alternatives.

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Understanding Thermal Loss in SiC MOSFET Designs

Conduction and Switching Loss – What Matters Most

Engineers already know the fundamentals:

• Conduction loss rises with current and RDS(on).

• Switching loss is tied to voltage, energy per cycle, and frequency.

Where SiC differentiates itself is maintaining low RDS(on) across temperature and significantly lower QG, reducing both conduction and switching losses under real operating conditions.

FUYI’s platforms show:

• 1200 V G2 RDS(on): 0.30–0.50 Ω

• 1700 V G2 RDS(on): 0.60–0.85 Ω

• FoM (RDS × QG): down to 3.456 — ahead of multiple industry competitors

These characteristics directly translate into lower junction temperatures in hard-switched inverter stages.

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FUYI 1200V and 1700V SiC MOSFET Performance: Thermal Specifications & Analysis

Thermal Performance Summary

Specification	FUYI 1200V SiC G2	FUYI 1700V SiC G2	Competing Solution (1200V)
On-Resistance (RDSON)	0.30–0.50Ω	0.60–0.85Ω	Higher across both classes
Gate Charge (QG)	12–18nC	18–24nC	Typicaly higher
Figure of Merit (FoM)	3.456–4.176	4.176–5.680	4.5–7.5 typical
Leakage Current (IDSS)	0.01µA (typical)	0.01µA (typical)	0.1–100µA

Key takeaways:

• Lower FoM means reduced switching loss and cooler operation at high frequencies.

• Ultra-low leakage improves high-temperature stability and reduces standby losses.

• Breakdown margin (BVDSS) is strong: 1500 V for 1200 V class, 2200 V for 1700 V class.

Real-World Thermal Interpretation

At typical inverter operating points (20 kHz, 50 A, 600 V bus):

• FUYI’s lower RDS(on) and FoM can reduce total device loss by 25–35 per cent.

• Lower total dissipation creates more thermal headroom under high ambient or transient load.

That margin becomes valuable in hot environments (e.g., 60°C PV inverters, EV engine bays).

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Bare Die vs Discrete Packages – Thermal Impact

FUYI supports both discrete packages (TO-247, TOLL, D2Pak) and bare die for custom module integration.

When to use discrete packages

• Fast prototyping

• Low/medium power ranges

• Simplified heat-sink design

θJC ≈ 0.35°C/W is typical for TO-247 packages.

When bare die offers advantages

• High-volume EV or industrial traction modules

• Highest power density

• Custom cooling architectures

Through sintered silver attach and aluminium nitride substrates: θJC can drop to 0.08–0.10°C/W, unlocking significantly better thermal efficiency.

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Practical Thermal Management Strategies

Engineers know that device performance is only one part of the thermal story. Three system-level techniques consistently produce strong results:

1. Heat sink and TIM optimisation

• Use TIMs with low thermal resistance

• Ensure good surface flatness and pressure

• Maintain θCS below ~0.20°C/W for TO-247 devices

2. Multi-device and multi-phase layouts

Spreading devices across heat-sink area improves thermal uniformity. Parallel devices need matched gate drive and symmetrical layout.

3. PCB-level thermal design

• Short, low-inductance loops

• Thermal vias under packages

• Balanced current distribution in multi-phase designs

These design techniques often save more thermal budget than simply upsizing the heat sink.

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Case Study: SiC vs IGBT in EV Inverter Applications

A simplified comparison highlights thermal benefits clearly:

Parameter	IGBT	SiC (FUYI 1200 V)
Switching frequency	10 kHz	20–40 kHz
Switching loss	High	Significantly lower
Total dissipation @120 kW	~8.5 kW	~5.2 kW
Cooling requirement	Larger radiator	Smaller / lower flow needed
Junction temperature	Higher under load	Lower, with more margin

System benefits:

• 1.5–2% inverter efficiency gain

• Less aggressive cooling design

• Improved reliability from reduced thermal cycling

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Competitive Analysis: How FUYI's Performance Compares Across Voltage Classes

FoM leadership

FUYI’s G2 platform achieves FoM values significantly below many competitors. Lower FoM = lower switching loss = lower junction temperature.

Ultra-low IDSS

IDSS around 0.01 µA is a key differentiator. This improves thermal stability at high temperatures and reduces standby loss.

Roadmap confidence

G3 devices begin delivering:

• 40% lower specific on-resistance

• Enhanced 37 V gate robustness

• Availability for 1200 V now and 1700 V later in the roadmap

This positions FUYI strongly for next-gen inverter architectures.

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G3 SuperGate: Next-Generation Thermal Efficiency

FUYI's next-generation G3 SuperGate technology represents a transformative advancement in SiC MOSFET thermal performance, building on proven G2 platform maturity with 40+ per cent reduction in specific on-resistance (RSp) across the complete voltage class portfolio.

G3 Specific On-Resistance Performance

The following table compares G2 and G3 thermal efficiency across FUYI's voltage platform:

Voltage Class	G2 RSp (mΩ·cm²)	G3 RSp (mΩ·cm²)	RSp Improvement	Current Density (A/mm²)	Gate Voltage
650V	3.2	1.9	40.6% ↓	5.9	37V
1200V	4.2	2.5	40.5% ↓	4.5	37V
1700V	7.2	4.2	41.7% ↓	TBD	37V
3300V	12.7	8.2	35.4% ↓	TBD	37V

Thermal Impact in EV Inverter Applications

For the 150kW EV inverter thermal scenario previously analysed, G3 deployment delivers cumulative efficiency gains:

G2 Platform (Current Baseline): 2.1kW total dissipation (1.8kW conduction + 0.3kW switching)

G3 Platform (Next-Generation): 1.38kW total dissipation (1.08kW conduction + 0.3kW switching)

This 34 per cent absolute reduction enables:

• Passive heat sink downsizing from 0.3°C/W to 0.5°C/W (45 per cent cost reduction in cooling infrastructure)

• Elimination of active cooling fans (reducing parasitic power draw and system complexity)

• Additional 15°C thermal margin above target 110°C junction temperature for automotive mission-profile uncertainties

• Extended component lifetime and improved overall system MTBF

Enhanced Gate Voltage Robustness

G3 introduces 37V gate voltage rating (versus 31V in G2), providing 19.4 per cent additional margin against gate-drive transients. This enhancement particularly benefits:

• Industrial motor drives with high dI/dt switching and EMI environments

• Paralleled MOSFET arrays prone to gate-drive asymmetry failures

• Harsh-environment applications requiring additional reliability headroom

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Conclusion: Thermal-Optimised Design as Competitive Advantage

FUYI’s 1200 V and 1700 V SiC MOSFET platforms offer strong thermal advantages through superior FoM values, low leakage, and robust architecture.

Whether you need a discrete device for an industrial inverter or bare die for high-volume EV traction modules, these platforms provide meaningful thermal headroom and efficiency gains.

For device selection, thermal evaluation samples, or design review support, Contact Ineltek Today 

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FAQ Section

Q: What is the real thermal advantage of SiC over traditional silicon MOSFET designs?

A: At equivalent voltage ratings, SiC MOSFETs deliver 30–50 per cent lower conduction losses (through superior RDSON) and 25–40 per cent lower switching losses (through lower gate charge). In practical inverter designs, total dissipation reduction of 35–45 per cent is achievable. The primary advantage compounds at higher temperatures, where silicon MOSFET performance degrades whilst SiC maintains efficiency. For EV applications, this translates to 2–3 per cent system efficiency improvement and 50–100km extended range.

Q: How do bare die options improve thermal performance compared to discrete packages?

A: Bare die enables custom substrate materials (aluminium nitride provides 170W/mK vs 0.3W/mK for FR-4), optimised die attachment (sintered silver ~0.15°C/W vs solder ~0.25°C/W in packages), and direct thermal paths to system-level cooling architecture. Achievable thermal resistance improves from ~0.35°C/W (package die-to-case) to ~0.08°C/W (custom module), representing a 75 per cent reduction. For high-volume applications, this investment pays dividends through reduced heat sink size and cooling complexity.

Q: What junction temperature should I design for with FUYI devices?

A: FUYI SiC MOSFETs are rated to 150°C maximum junction temperature. Industrial design practice typically targets 20–30°C margin below absolute maximum, establishing 120–130°C as design ceiling. This ensures:

• Thermal stability across manufacturing tolerances and component aging

• Margin for worst-case ambient temperature excursions

• Adequate headroom for transient peak power events

• Extended component lifespan (semiconductor reliability doubles approximately every 10°C temperature reduction)

For automotive applications, even more conservative 100–110°C design ceilings may be appropriate, depending on vehicle thermal environment and long-term reliability targets.

Q: Why does FUYI's leakage current matter?

A: Low leakage improves thermal stability and efficiency during standby and partial-load conditions. FUYI achieves IDSS of 0.01µA typical (100x lower than competitor standards of 1–10µA). In battery-powered or standby-mode applications, this translates to measurable power savings. For a device operating in standby 20 hours daily with 48V supply:

• Competitor 1µA IDSS: 1µA × 48V × 20hrs/day = 960µWh daily loss

• FUYI 0.01µA IDSS: 0.01µA × 48V × 20hrs/day = 9.6µWh daily loss Annual savings: ~300mWh per device. In systems with multiple devices or extended mission profiles, this becomes significant.